Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

• 3 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, memory subsystems and UPF.

• 3 years of experience in SoC power design.

Preferred qualifications:

• Master's degree in Electrical Engineering, or equivalent practical experience.

• Experience in UPF development of IP, Sub-system or SoC.

• Experience with low power design techniques and methodologies.

• Understanding of Low Power Synthesis and Place and route (PnR) flows.

• Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Work with Architect, Microarchitecture, and Register-Transfer Level (RTL) design teams on capturing power intent and convergence.

• Review the front-end low power static checks and drive Unified Power Format (UPF) and VCLP convergence and Signoff.

• Support RTL and Design for Testing (DFT) teams on the UPF aspect in incorporating Physical Design team feedback.

• Be an interface to cross-domains such as DFT, Domain Validation (DV), and RTL in addressing any UPF/power intent related methodology and issues.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.